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| PRODUCT SPECIFICATIONS (R) Integrated Circuits Group LH28F160S3HT-L10A 16M (2MB x 8/1MB x 16) (Model No.: LHF16KA7) Flash Memory Spec No.: EL127111A Issue Date: August 29, 2000 SHARP .LHF16KA7 - l Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). i *Office electronics l instrumentation and measuring equipment l Machine tools aAudiovisual equipment *Home appliance l Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. -Control and safety devices for airplanes, trains, automobiles, and other transportation equipment *Mainframe computers l Tcaffic control systems aGas leak detectors and automatic cutoff devices *Rescue and security equipment @Othersafety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. aAerospace equipment l Communications equipment for trunk lines l Control equipment for the nuclear power industry l Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. l Please direct all queries regarding the products covered herein to a sales representative of the company. Rev.1.9 SHARP ._-- LHF16KA7 1 CONTENTS PAGE I INTRODUCTION ...................................................... 1.1 Product Overview.. .............................................. 2 PRINCIPLES OF OPERATION ................................ 2.1 Data Protection ................................................... 3 BUS OPERATION.. .................................................. 3.1 Read ................................................................... 3.2 O&put Disable .................................................... 3.3 3.4 3.5 3.6 3.7 Standby.. ............................................................. Deep Power-Down .............................................. Read Identifier Codes Operation.. ....................... Query Operation .................................................. Write.. .................................................................. 3 3 6 7 7 7 7 7 7 8 8 8 8 11 11 11 11 12 12 13 13 14 14 15 15 16 16 17 PAGE 5 DESIGN CONSIDERATIONS ................................ .3C 5.1 Three-Line Output Control ................................ .3C 5.2 STS and Block Erase, Full Chip Erase, (Multi) Word/Byte Write and Block Lock-Bit Configuration Polling ................................................................ 5.3 Power Supply Decoupling .................................. 5.4 V,, Trace on Printed Circuit Boards.. ............... 5.5 Vcc, V,,,, RP# Transitions.. .............................. 5.6 Power-Up/Down Protection.. ............................. 5.7 Power Dissipation ............................................. 3c 3c .3C .31 .31 .31 6 ELECTRICAL SPECIFICATIONS.. ........................ .3i 6.1 Absolute Maximum Ratings .............................. .3i 6.2 Operating Conditions ......................................... 32 6.2.1 Capacitance ................................................. 32 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 AC Input/Output Test Conditions.. ............... .3Z DC Characteristics ........................................ 34 AC Characteristics - Read-Only Operations .3E AC Characteristics - Write Operations.. ....... .3E Alternative CE#-Controlled Writes.. ............. .41 Reset Operations ........................................ .4Z Block Erase, Full Chip Erase, (Multi) Word/Byte Write and Block Lock-Bit Configuration Performance.. ........................ .44 4E 46 1 COMMAND DEFINITIONS.. ..................................... 4.1 Read Array Command ....................................... 4.2 Read Identifier Codes Command ...................... 4.3 Read Status Register Command.. ..................... 4.4 Clear Status Register Command.. ..................... 4.5 Query Command ............................................... 4.51 Block Status Register .................................. 4.5.2 CFI Query Identification StAng.. ................... 4.5.3 System Interface.lnformation.. ..................... 4.5.4 Device Geometry Definition ......................... 4.5.5 SCS OEM Specific Extended Query Table.. 4.6 Block Erase Command.. .................................... 4.7 Full Chip Erase Command ................................ 4.8 Word/Byte Write Command.. ............................. 4.9 Multi Word/Byte Write Command ...................... 4.10 Block Erase Suspend Command.. ................... 7 ADDITIONAL INFORMATION ................................ 7.1 Ordering Information .......................................... 4.11 (Multi) Word/Byte Write Suspend Command ... 17 4.12 Set Block Lock-Bit Command.. ........................ 18 4.13 Clear Block Lock-Bits Command.. ................... 18 4.14 STS Configuration Command ......................... 19 Rev. 1.9 SHAl?P LHFlGKA7 - 2 LH28F160S3HT-Ll OA 1 GM-BIT (2MBx8/1 MBxl6) Smart 3 Flash MEMORY n Smart 3 Technology - 2.7V or 3.3V Vcc - 2.7V, 3.3V or SV Vpp I I Common Flash Interface (CFI) - Universal & Upgradable Interface Scalable Command Set (SCS) n Enhanced Data Protection Features - Absolute Protection with VpP=GND - Flexible Block Locking - Erase/Write Lockout during Power Transitions n High Speed Write Performance - 32 Bytes x 2 plane Page Buffer - 2.7 @Byte Write Transfer Rate n High Speed Read Performance - 1OOns(3.3V*O.3V), 120ns(2.7\1-3.6V) I Operating Temperature - -40C to +85X n Extended Cycling Capability - 100,000 Block Erase Cycles - 3.2 Million Block Erase Cycles/Chip n Low Power Management - Deep Power-Down Mode - Automatic Power Savings Mode Decreases ICC in Static Mode n Automated Write and Erase - Command User Interface - Status Register n Industry-Standard Packaging - 56-Lead TSOP n ETOgTM* V Nonvolatile Technology Flash n Enhanced Automated Suspend Options - Write Suspend to Read - Block Erase Suspend to Write - Block Erase Suspend to Read n High-Density Symmetrically-Blocked Architecture - Thirty-two 64K-byte Erasable Blocks I I SRAM-Compatible User-Configurable Write Interface x8 or x16 Operation n CMOS Process (P-type silicon substrate) n Not designed or rated as radiation hardened SHARP's LH28F160S3HT-LlOA Flash memory with Smart 3 technology is a high-density, low-cost, nonvolatile, *cad/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for resident flash arrays, SlMMs and memory :ards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F160S3HT-LlOA offers three levels of protection: absolute protection with V,, at ?ND, selective hardware block locking, or flexible software block locking. These alternatives give designers Jltimate control of their code security needs. The LH28F160S3HT-LlOA is conformed to the flash Scalable Command Set (SCS) and the Common Flash nterface (CFI) specification which enable universal and upgradable interface, enable the highest system/device data transfer rates and minimize device and system-level implementation costs. The LH28F160S3HT-LlOA is manufactured on SHARP's 0.35um ETOX TM* V process technology. ndustry-standard package: the 56-Lead TSOP ideal for board constrained applications. `ETOX is a trademark of Intel Corporation. It come in Rev. 1.9 SHARP .1 INTRODUCTION This datasheet contains LH28F160S3HT-Ll OA specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LHFlGKA7 3 write suspend mode enables the system to read data or execute code from any other flash memory array location. 1 1.l Product Overview The LH28F160S3HT-Ll OA is a high-performance 16M-bit Smart 3 Flash memory organized as 2MBx80MBxl6. The 2MB of data is arranged in thirty-two 64K-byte blocks which are individually erasable, lockable, and unlockable in-system. The memory map is shown in Figure 3. Smart 3' technology provides a choice of V,, and V,, combinations, as shown in Table 1, to meet system performance and power expectations. 2.7V Vc, consumes approximately one-fifth the power of 5V Vc,. V,, at 2.7V, 3.3V and 5V eliminates the need for a separate 12V converter, while V,,=5V maximizes erase and write performance. In addition to flexible erase and program voltages, the dedicated V,, pin gives complete data protection when Individual block locking uses a combination of bits and WP#, Thirty-two block lock-bits, to lock ant unlock blocks. Block lock-bits gate block erase, full chip erase and (multi) word/byte write operations. Block lock-bit configuration operations (Set Block Lock-Bit and Clear Block Lock-Bits commands) sei and cleared block lock-bits. The status register indicates when the WSM's block erase, full chip erase, (multi) word/byte write or block lock-bit configuration operation is finished. The STS output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status maskins (interrupt masking for background block erase, fol example). Status polling using STS minimizes bott CPU overhead and system power consumption. STS pin can be configured to different states using the Configuration command. The STS pin defaults tc RY/BY# operation. When low, STS indicates that the WSM is performing a block erase, full chip erase (multi) word/byte write or block lock-bit configuration STS-High Z indicates that the WSM is ready for a new command, block erase is suspended and (multi: word/byte write are inactive, (multi) word/byte write are suspended, or the device is in deep power-dowr mode. The other 3 alternate configurations are al pulse mode for use as a system interrupt. The access time is 100ns (tAVQv) over the extendec temperature range (-40C to +85"C) and Vc, suppI\ voltage range of 3.OV-3.6V. At lower V,, voltage, the access time is 120ns (2.7V-3.6V). The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS m`ode, the typical I,,, current is 3 mA at 3.3V V,c. When either CE,# or CE,#, and RP# pins are at V,, the I,, CMOS standby mode is enabled. When the RP# pin is at GND, deep power-down mode ic enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHav) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. The device is available in 56-Lead TSOP (Thin Small Outline Package, 1.2 mm thick). Pinout is shown in Figure 2. Table 1. Vcc and Vpp Voltage Combinations Offered by Smart 3 Technology Vcc Voltage Vpp Voltage 2.7V 2.7V, 3.3V, 5V 3.3v 3.3v, 5v detection Circuitry Internal and VP, VW automatically configures the device for optimized read and write operations. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations. 4 block erase operation erases one of the device's %lK-byte blocks typically within 0.41s (3.3V Vcc, 5V VP,) independent of other blocks. Each block can be independently erased 100,000 times (3.2 million olock erases per device). Block erase suspend mode allows system software to suspend block erase to read or write data from any other block. A word/byte write is performed in byte increments typically within 12.95ps (3.3V V,,, 5V VP,). A multi word/byte write has high speed write performance of 2.7@byte (3.3V V,,, 5V VP,). (Multi) Word/byte Rev. 1.9 SHARP LHFlGKA7 4 Cl3 WEX OE% RP# WP# I/ Comparator +b II-4 I Figure 1. Block Diagram NC kE,# NC ./ Azo AIS Al6 A17 Al6 VCC A15 Al.4 A13 Al2 CEo# VPP RP# 41 AIO As Ae GND A7 As A5 2 A2 AI d 3 4 5 6 `7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 : ----G-L 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 WP# WE# OE# STS DQ15 z:, DQ6 GND DQ13 DQ5 DQ12 56 LEAD TSOP STANDARD PINOUT 14mm x 20mm TOP VIEW DQ4 vcc GND DQll DQ3 DQlo DQz vcc DQP DQ; 1 I I ) DQe DQo A0 BYTE# NC NC Figure 2. TSOP 56-Lead Pinout (Normal Bend) Rev. 1.9 SHARP _LHF16KA7 Table 2. Pin Descriptions T Name and Function ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. Ao: Byte Select Address. Not used in x16 mode(can be floated). AI-AK Column Address. Selects 1 of 16 bit lines. A+Ai5: Row Address. Selects 1 of 2048 word lines. A164420 : Block Address. DATA INPUT/OUTPUTS: DQo-DQ,:lnputs data and commands during CUI write cycles; outputs data during memory array, status register, query, and identifier code read cycles. Data pins float to highimpedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. DQs-DQ15:lnpUtS data during CUI write cycles in x16 mode; outputs data during memory array read cycles in xl 6 mode; not used for status register, query and identifier code read mode. Data pins float to high-impedance when the chip is deselected, outputs are disabled, or in x8 mode(Byte#=V,, ). Data is internally latched during a write cycle. CHIP ENABLE: Activates the device's control logic, input buffers decoders, and sense amplifiers. Either CE,# or CE,# V,, deselects the device and reduces power consumption to standby levels. Both CE,-# and CE,# must be V,, to select the devices. RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal automation. RP# V,, enables normal operation. When driven \JIL, RP# inhibits write operations which provides data protection during power transitions. Exit from deep power-down sets the device to read array mode. OUTPUT ENABLE: Gates the device's outputs during a read cycle. WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE# pulse. STS (RY/BY#): Indicates the status of the internal WSM. When configured in level mode (default mode), it acts as a RY/BY# pin. When low, the WSM is performing an internal operation (block erase, full chip erase, (multi) word/byte write or block lock-bit configuration). STS High Z indicates that the WSM is ready for new commands, block erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is suspended or the device is in deep power-down mode. For alternate configurations of the STATUS pin, see the Configuration command. WRITE PROTECT: Master control for block locking. When V,,, Locked blocks can not be erased and programmed, and block lock-bits can not be set and reset. BYTE ENABLE: BYTE# V,, places device in x8 mode. All data is then input or output on DQO-,, and DQse15 float. BYTE# V,, places the device in x16 mode , and turns off the A, input buffer. BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCKBIT CONFIGURATION POWER SUPPLY: For erasing array blocks, writing bytes or configuring block lock-bits. With V+V+~,K, memory contents cannot be altered. Block erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an invalid vpp (see DC Characteristics) produce spurious results and should not be attempted. DEVICE POWER SUPPLY: Internal detection configures the device for 2.7" or 3.3" operation. To switch from one voltage to another, ramp V,, down to GND and then ramp V,, to the new voltage. Do not float any power pins. With V,,IV,,,, all write attempts to the flash memory are inhibited. Device operations at invalid V,, voltage (see DC Characteristics) produce spurious results and should not be attempted. GROUND: Do not float any ground pins. NO CONNECT: Lead is not internal connected; it may be driven or floated. 5 I Type *o-*20 INPUT x&)-DC+! INPUT/ 3UTPUT I CEO% CE,# INPUT RP# OE# WE# INPUT INPUT INPUT STS OPEN DRAIN OUTPUT WP# BYTE# tWPUT lNPUT "PP SUPPLY "cc GND NC I SUPPLY SUPPLY Rev. 1.9 SHARP .r .i LHFlGKA7 6 1 64K-byte Block 3'1 2 PRINCIPLES OF OPERATION The LH28F160S3HT-Ll OA Flash memory includes an on-chip WSM to manage block erase, full chip erase, (multi) word/byte write and block lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, and minimal processor overhead with RAM-Like interface timings. After initial device power-up or return from deep power-down mode (see Bus Operations), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations. Status :egister, query structure and identifier codes can be accessed through the CUI independent of the V,, voltage. High voltage on VPP enables successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. All functions associated with altering memory contents-block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, status, query and identifier codes-are accessed via the CUI and verified through the status register. written using standard Commands are microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, full chip erase, (multi) word/byte write and block lockbit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, and margining of data. internal verification, Addresses and data are internally latch during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, outputs query structure or outputs status register data. Interface software that initiates and polls progress of block erase, full chip erase, (multi) word/byte write and block lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read or write data from any other block. Write suspend allows system software to suspend a (multi) word/byte write to read data from any other flash memory array location. 1AFFFF 1 AOOW ISFFFF 1SOOCKl 1SFFFF laOW0 17FFFF 17OmO IGFFFF 160000 15FFFF 15OoM) 14FFFF 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-byte Block 64K-bvte Block Figure 3. Memory Map 26 25 24 23 22 21 20 19 `81 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14oooo 13FFFF ,-mm IPFFFF 4~cyyI 1lFFFF 11ocw 1OFFFF lcmoa OFFFFF OFOOOO OEFFFF OEOOOO OIJFFFF ODoooO OCFFFF ocoooo OBFFFF OAFFFF OAOWO OSFFFF OSOWO 08FFFF OKCOO 07FFFF 07wOo OGFFFF 060000 OBFFFF nE-n 04FFFF 04OWO OIFFFF 03Ocm OZFFFF OZWOO 01 FFFF 01wo0 OOFFFF L Rev. 1.9 SHARP LHFlGKA7 - 7 2.1 Data Protection Depending on the application, the system designer may choose to make the V,, power supply switchable (available only when block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are required) or hardwired to VPPH1,2/3. The device accommodates either design practice and encourages optimization of the processor-memory interface. contents cannot be altered. The CUI, with multi-step block erase, full chip erase, (multi) word/byte write and block lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage,is applied to V,,. All write functions are disabled when Vcc is below the write lockout voltage V,,, or when RP# is at V,,. The device's block locking capability provides additional protection from inadvertent code or data alteration by gating block erase, full chip erase and (multi) word/byte write operations. 3.2 Output Disable With OE# at a logic-high level (VI,), the devict outputs are disabled. Output pins DO,-DQ,, an placed in a high-impedance state. -l 3.3 Standby Either CE,# or CE,# at a logic-high level (V,,) place: the device in standby mode which substantiall! reduces device power consumption. DQo-DQ,, outputs are placed in a high-impedance statt independent of OE#. If deselected during bloc1 erase, full chip erase, (multi) word/byte write ant block lock-bit configuration, the device continue: functioning, and consuming active power until the operation completes. When Vpp~VppLKtmemory 3.4 Deep Power-Down RP# at V,, initiates the deep power-down mode. 3 BUS OPERATION The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. In read modes, RP#-low deselects the memory places output drivers in a high-impedance state ant turns off all internal circuits. RP# must be held low fol a minimum of 100 ns. Time t,,crv is required after return from power-down until initial memory access outputs are valid. After this wakeup interval, norma operation is restored. The CUI is reset to read arra) mode and status register is set to 80H. During block erase, full chip erase, (multi) word/byte write or block lock-bit configuration modes, RP#-low will abort the operation. STS remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tPHWL is required after RP# goes to logic-high (V,,) before another command can be written. As with any automated device, it is important tc assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP's flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. 3.1 Read Information can be read from any block, identifier codes, query structure,`or status register independent of the V,, voltage. RP# must be at VI,. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, Query or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. Five control pins dictate the data flow in and out of the component: CE# (CE,#, CE,#), OE#, WE#, RP# and WP#. CE,#, CE,# and OE# must be driven active to obtain data at the outputs. CE,#, CE,# is the device selection control, and when active enables the selected memory device. OE# is the data output (DC&-DQ,,) control and when active drives the selected memory data onto the I/O bus. WE# and RP# must be at V,,. Figure 17, 18 illustrates a read cycle. Rev. 1 .Q _I -- LHFlGKA7 3.6 Query Operation 8 3.5 Read Identifier Codes Operation The read identifier codes operation outputs the manufacturer code, device code, block status codes for each block (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. The block status codes identify locked or unlocked block setting and erase completed or erase uncompleted condition. The query operation outputs the query structure. Query database is stored in the 48Byte ROM. Query structure allows system software to gain critical information for controlling the flash component. Query structure are always presented on the lowestorder data output (DQc-DQ,) only. 3.7 Write Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When Vcc=Vcc1,2 and VPP=VPPHt/2/3, the CUI additionally controls block erase, full chip erase, (multi) wordlbyte write and block lock-bit configuration. The Block Erase command requires appropriate command data and an address within the block to be erased. The Word/byte Write command requires the command and address of the location to be written. Set Block Lock-Bit command requires the command and block address within the device (Block Lock) to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Figures 19 and 20 illustrate WE# and CE#-controlled write operations. 1FFFFF :.. : '. :> :. .: ,;.' . . .,. . . . 1;; ,, ... ..A.. '. .' j.: R&&&&, ,., .,:,': .:' .: '. ,: :... Future ~+irnentatt~n ;. ,Fm; .. :. ,K)oo5 iilr-' l_l..d+ - -----------_-------1---l !", :'.. ;. Block 31 Status Code IF0004 ,Fooo3 T---,-. ~_____ --; ____T-------y---I JGxwv~d for ;. tfutye h$e.merrtiian B&;k31 : ,Foooo :,.., :`i: IEFFFF;:. :' . ; : ':,,.. :: :. m.. w. : . '(~ioiks2thi~gl-l~) 02oooo; :. ,+ ..: ,, '. ', : OlFFFF ', " : ..,I. ; ,:" "') ; .,. :. o,o(y& (I " y., l---l-l---l-~--l'l-l----rll---lll-l--------01ooo5 ./' Block 1 Status Code 010004 ___________ --- ______ ---__---------010003i&e&ed~for ,: . . .. : .; :...:.f;uture:`tmplemen~tiQn .. 01~ 1. .,: .' `., Block" OOFFFF ;. 1. 4 COMMAND DEFINITIONS When the V,, voltage I V,,,,, Read operations from the status register, identifier codes, query, or blocks are enabled. Placing V,,,,,us on V,, enables successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 4 defines these commands. Resewed far Future Implementation ooooO6___- -- ____-- ____--------_-----. -----coo005 Block 0 Status Code OoOcQ4 _____-_____-_______-----------------OOanI3 Device Code OOmO2 ____________________----------------oooQo1 Manufacturer Code Figure 4. Device Identifier Block ( Code Memory Map Rev. 1.9 SHARP _= LHFlGKA7 Table 3. Bus Operations(BYTE#=V,Uj CE"# CE,# OE# WE# 1 Address RP# V,, V,, V,, V,H X v,w V,, V,w V,H X V,, V,H v 11 v,,, 1 X See Figure 4 See Table 7-11 I 9 Mode Read Output Disable Notes 1,2,3,9 3 1 Vpp X X 1 DQnm15 1 STS D&r X High Z X jeep Power-Down lead Identifier Lodes Query I 4 9 9 I V,, VI, vlH I X %L VI, I X %L 4, I X 4, VI, I X 4, vlH 1 VII X X x 1 x 1 High Z Note 5 Note 6 DIN I High Z High Z High Z x Write 1 3,7&W 1 `.`,H 1 VII 1 VII 1 VI'I X VI, Deep Power-Down Read Identifier Codes Query 4 9 9 VI, `1, `1, X VlL VI, V,w X VI, VI, X YL VI, X `1, vlH X DIN X VII VII V,H VII 3,7,8,9 VI,, Write NOTES: memory contents can be read, but not altered. 1. Refer to DC Characteristics. When V&f,,,,, 2. X can be V,, or VrH for control pins and addresses, and VP,,, or VPr+rt/2/s for V,,. See DC Characteristics for bPLK and VPPH1/~3 voitagese X See Figure 4 SeeTable 7-11 X X X x High Z Note 5 Note 6 High Z High Z High Z 3. STS is V,, (if configured to RY/BY# mode) when the WSM is executing internal block erase, full chip erase, (multi) word/byte write or block lock-bit configuration algorithms. It is floated during when the WSM is not busy, in block erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or . deep power;down mode. 4. RP# at GN&O.2V ensures the lowest deep power-down current. 5. See Section 4.2 for read identifier code data. 6. See Section 4.5 for query data. 7. Command writes involving block erase, full chip erase, (multi) word/byte write or block lock-bit configuration are reliably executed when Vpp=VPPH1/2/3 and Vcc=Vcc1~2. 8. Refer to Table 4 for valid D,, during a write operation. 9. Don't use the timing both OE# and WE# are VI,. , Rev. 1.9 SHARP .- LHFlGKA7 10 I Command Read Array/Reset .i Table 4. Command Definitions(l") Bus Cycles Notes First Bus Cycle Oper(`) 1 Add&*) 1 Data13) Req'd 1 Write ( X 1 FFH 22 4 Write X 90H Write X 98H 22 2 Write X 70H Write X 5 Write BA 2 Write X 2 2 Write WA 55 Second Bus Cycle Ope#) 1 Addr(*) 1 Data13) Read Read Read IA QA X I T _.._. C `D II 4lternate Word/Byte Write Write WA WD 2 Write WA 10H 596 SetupWrite Multi Word/Byte Write Write WA N-l 9 Write WA E8H 24 Setup/Confirm Block Erase and (Multi) 5 Write X BOH 1 Word/byte Write Suspend Confirm and Block Erase and Write X DOH 1 5 (Multi) Word/byte Write Resume Write BA 7 Write BA 60H OlH Block Lock-Bit Set Setup/Confirm 2 Block Lock-Bit Reset 60H Write X DOH 2 8 Write X Setup/Confirm STS Configuration Write X B8H Write X OOH 2 Level-Mode for Erase and Write (RY/BY# Mode) STS Configuration Write X B8H Write X OlH 2 Pulse-Mode for Erase STS Configuration 2 Write X B8H Write X 02H Pulse-Mode for Write STS Configuration Write X 03H 2 Write X B8H Pulse-Mode for Erase and Write NOTES: 1. BUS operations are defined in Table 3 and Table 3.1. 2. X=Any valid address within the device. IA=ldentifiep Code Address: see Figure 4. QA=Quety Offset Address. BA=Address within the. block being erased or locked. WA=Address of memory location to be written. 3. SRD=Data read from status register. See Table 14 for a description of the status register bits. WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID=Data read from identifier codes. QD=Data read from query database. 4. Following the Read Identifier Codes command, read operations access manufacturer, device and block status codes. See Section 4.2 for read identifier code data. 5. If the block is locked, WP# must be at VI, to enable block erase or (multi) word/byte write operations. Attempts to issue a block erase or (multi) word/byte write to a locked block while RP# is VI,. 6. Either 40H or 10H are recognized by the WSM as the byte write setup. 7. A block lock-bit can be set while WP# is VI,. 8. WP# must be at VI, to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. 9. Following the Third Bus Cycle, inputs the write address and write data of `N' times. Finally, input the confirm command `DOH'. 10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. Rev. 1.9 SHARI= .-- LHF16KA7 4.3 Read Status Register Command 11 4.1 Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend and (Multi) Word/byte Write Suspend command. The Read Array command functions independently of the VP,, voltage and RP# must be Vi,* The statusregister may be read to determine when i block erase, full chip erase, (multi) word/byte write OI block lock-bit configuration is complete and whethei the operation completed successfully(see Table 14) It may be read at any time by writing the Read Statu: Register command. After writing this command, al subsequent read operations output data from the status register until another valid command is written The status register contents are latched on the fallins edge of OE# or CE#(Either CE,# or CE,#) whichever occurs. OE# or CE#(Either CE,# or CE,#: must toggle to `Jr, before further reads to update the status register latch. The Read Status Register command functions independently of the V,, voltage RP# must be VI,. The extended status register may be read tc determine multi word/byte write availability(see Table 14.1). The extended status register may be read a any time by writing the Multi Word/Byte Write command. After writing this command, all subsequen read operations output data from the extended statuz register, until another valid command is written. Mult Word/Byte Write command must be re-issued tc update the extended status register latch. 4.2 F&ad Identifier Codes Command The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Figure 4 retrieve the manufacturer, device, block lock configuration and block erase status (see Table 5 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the V,, voltage and RP# must be V,,. Following the Read Identifier Codes command, the following information can be read: Table 5. Identifier Codes Address Data Code 00000 Manufacture Code BO 00001 ./ 00002 Device Code 00003 x0004(' ) Block Status Code x0005(`) ~ *Block is Unlocked DC&,=0 l Block is Locked DQc= 1 *Last erase operation 1 / DQ,=O 1 completed successfully @Last erase operation did DQ,=l not completed successfully OReserved for Future Use DQyw7 NOTE: 1. X selects the specific block status code to be read. See Figure 4 for the device identifier code memory map. 4.4 Clear Status Register Command Status register bits SR.5, SR.4, SR.3 and SR.l are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 14). By allowins system software to reset these bits, severa operations (such as cumulatively erasing or lockinc multiple blocks or writing several bytes in sequence: may be performed. The status register may be pollee to determine if an error occurs during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied V,, Voltage. RP# must be VI,. This command is not functional during block erase, ful chip erase, (multi) word/byte write block lock-bii configuration, block erase suspend or (multi: word/byte write suspend modes. Rev. 1.9 SHARP .-- LHFlGKA7 Table 6. Example of Query Structure ( Mode Off set Address ou DQ%8 A,, A,, A,, A,, A,, A, 1 , 0 , 0 , 0 (0 , 0 (20H) High Z X8 mode 1 , 0 , 0 , 0 , 0 , 1 (21H) High Z 1, O,O,O,l ,0(22H) HighZ 1 , 0 , 0 , 0 , 1 , 1 (23H) High Z A,, A,, A,, A,, A, X16mode 1 ,O,O,O,O (10H) OOH l,O,O,O,l (11H) OOH 12 1.5 Query Command =luery database can be read by writing Query :ommand (98H). Following the command write, read ycle from address shown in Table 7-l 1 retrieve the xitical information to write, erase and otherwise :ontrol the flash component. A, of query offset address is ignored when X8 mode (BYTE#=V,L). ;luery data are always presented on the low-byte jata output (DC&-D&). In x16 mode, high-byte ;DQs-DQ,s) outputs OOH. The bytes not assigned to any information or reserved for future use are set to `0". This command functions independently of the Jpp voltage. RP# must be V,,. But DQm-, "Q" "Q" "R" "R" "Q" "R" 1.5.1 Block Status Register This field provides lock configuration and erase status for the specified block. These informations are only available Nhen device is ready (SR.7=1). If block erase or full chip erase operation is finished irregulary, block erase status lit will be set to "1". If bit 1 is "l", this block is invalid. Table 7. Query Block Status Register Offset (Word Address) (BA+2)H Length OlH Description Block Status Register bit0 Block Lock Configuration O=Block is unlocked 1=Block is Locked bit1 Block Erase Status O=Last erase operation completed successfully 1=Last erase operation not completed successfully t&2-7 reserved for future use v' Uote: I. BA=The beginning of a Block Address. Rev. 1.9 SHARP _-IS.2 LHFlGKA7 String 13 CFI Query Identification `he identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the spec and which Vendor-specified command set(s) is(are) upported. Table 8. CFI Query Identification Offset (Word Address) lOH,l lH,12H 13H,14H 15H.16H 17H,18H i lSH,lAH Length 03H 02H 02H 02H 02H String Description Query Unique ASCII string "QRY" 51 H,52H,59H Primary Vendor Command Set and Control Interface ID Code 01 H,OOH (SCS ID Code) Address for Primary Algorithm Extended Query Table 31 H,OOH (SCS Extended Query Table Offset) Alternate Vendor Command Set and Control Interface ID Code OOOOH (OOOOH means that no alternate exists) Address for Alternate Algorithm Extended Query Table 1OOOOH (OOOOHmeans that no alternate exists) 1.53 System Interface Information The following device information can be useful in optimizing system interface software. Table 9. System Information Offset (Word Address) 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 1 1 ./' Length OlH OlH OlH OlH .OlH 01 H OlH OlH OlH 01 H OlH OlH String Description Voc Logic Supply Minimum Write/Erase voltage 27H (2.7V) V,, Logic Supply Maximum Write/Erase voltage 55H (5.5V) V,, Programming Supply Minimum.Write/Erase voltage 27H (2.7V) Up,, Programming Supply Maximum Write/Erase voltage 55H (5.5V) Typical Timeout per Single Byte/Word Write I03H (23=8us) 1Typical Timeout for Maximum Size Buffer Write (32 Bytes) 06H (26=64us) Typical Timeout per Individual Block Erase OAH (OAH=lO 21=1024ms) Typical Timeout for Full Chip Erase OFH (OFH=15, 215=32768ms) Maximum Timeout per Single Byte/Word Write, 2N times of typical. I04H (24=1 6, 8usxl6=128us) 1Maximum Timeout Maximum Size Buffer Write, 2N times of typiCal. 04H (24=1 6, 64usxl6=1024us) Maximum Timeout per Individual Block Erase, 2N times of typical. 04H (24=1 6,1024msxl6=16384ms) Maximum Timeout for Full Chip Erase, 2N times of typical. _ I04H (24=1 6,32768msxl6=524288ms) Rev. 1.9 SHARI= _/ LHFlGKA7 14 .i 1.5.4 Device Geometry Definition rhis field provides critical details of the flash device geometry. Table 10. Device Geometry Offset (Word Address) 27H 28H,29H 2AH,2BH 2CH 2DH,2EH \ 2FH,30H Length OlH 02H 02H 01H 02H 02H Definition Description Device Size 15H (15H=21,221=20971 52=2M Bytes) Flash Device Interface description 02H,OOH (x8/x16 supports x8 and xl 6 via BYTE#) Maximum Number of Bytes in Multi word/byte write 05H,OOH (2s=32 Bytes ) Number of Erase Block Regions within device 01 H (symmetrically blocked) The Number of Erase Blocks 1FH,OOH (1 FH=31 ==> 31+1=32 Blocks) The Number of "256 Bytes" cluster in a Erase block , OOH,OlH (OlOOH=256 ==>256 Bytes x 256= 64K Bytes in a Erase Block) 1.5.5 SCS OEM Specific Extended Query Table Zertain flash features and commands may be optional in a vendor-specific algorithm specification. The optional rendor-specific Query table(s) may be used to specify this and other types of information. These structures are defined solely by the flash vendor(s). Tat e 11. SCS OEM Specific Extended Query Table Offset (Word Address) 31 H,32H,33H Length 03H OlH OlH 04H 38H,39H " Description PRI 50H,52H,49H 31 H (1) Major Version Number , ASCII 30H (0) Minor Version Number, ASCII OFH,OOH,OOH,OOH Optional Command Support bitO=l : Chip Erase Supported bit1 =l : Suspend Erase Supported bit2=1 : Suspend Write Supported bit3=1 : Lock/Unlock Supported bit4=0 : Queued Erase Not Supported bit531 =O : reserved for-future use OlH Supported Functions after Suspend bitO=l : Write Supported after Erase Suspend bit1 -7=O : reserved for future use 03H,OOH Block Status Register Mask bitO=l : Block Status Register Lock Bit [BSR.O] active bitl=l : Block Status Register Valid Bit [BSR.l] active bit2-15=0 : reserved for future use V,, Logic Supply Optimum Write/Erase voltage(highest performance) 50H@.OV) Vpp Programming Supply Optimum Write/Erase voltage(highest performance) 56i-l(5.OV) 3AH OlH 3BH,3CH 02H 3DH 3EH 3FH OlH OlH reserved deserved for future versions of the SCS Specification Rev. 1.9 .- LHFlGKA7 15 4.6 Block Erase Command Block erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 5). The CPU can detect block erase completion by analyzing the output data of the STS pin or status register bit SR.7. When t$e block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1 `I. Also, reliable block erasure can only occur when Vcc=Vcc1,2 and VPP=VPPH,,2/3. In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while V,, 1.7 Full Chip Erase Command This command followed by a confirm command ,DOH) erases all of the unlocked blocks. A full chip Rev.1.9 SHARP __- LHF16KA7 16 1 4.8 Word/Byte Write Command Word/byte write is executed by a two-cycle command sequence. Word/Byte Write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the word/byte write and write verify algorithms internally. After the word/byte write sequence is written, the device automatically outputs status register data when read (see Figure 7). The CPU can detect the completion of the word/byte write event by analyzing the STS pin or status register bit SR.7. When word/byte write is complete, status register bit SR.4 should be checked. If word/byte write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command. Reliable word/byte writes can only occur when Vcc=Vcc,,2 and VPP=VPPH112,3.In the absence of this high voltage, memory contents are protected against word/byte writes. If word/byte write is attempted while V+V,,,,, status register bits SR.3 and SR.4 will be set to "1". Successful word/byte write requires that the corresponding block lock-bit be cleared or, if set, that WP#=V,,. If word/byte write is attempted when the corresponding block lock-bit is set and WP#=V,,, SR.1 and SR.4 will be set to "1". Word/byte write operations with V,, 4.9 Multi Word/Byte Write Command Multi word/byte write is executed by at least fourycle or up to 35cycle command sequence. Up to 32 bytes in x8 mode (16 words in xl6 mode) can be oaded into the buffer and written to the Flash Array. =irst, multi word/byte write setup (E8H) is written with :he write address. At this point, the device automatically outputs extended status register data :XSR) when read (see Figure 8, 9). If extended status register bit XSR.7 is 0, no Multi Word/Byte Nrite command is available and multi word/byte write setup which just has been written is ignored. To retry, Rev. 1.9 SHARP .-- LHF16KA7 17 4.10 Block Erase Suspend Command The Block Erase Suspend command allows blockerase interruption to read or (multi) word/byte-write lata in another block of memory. Once the blockxase process starts, writing the Block Erase Suspend command requests that the WSM suspend :he block erase sequence at a predetermined point in :he algorithm. The device outputs status register data when read after the Block Erase Suspend command s written. Polling status register bits SR.7 and SR.6 zan determine when the block erase operation has ?een suspended (both will be set to "1"). STS will also transition to High Z. Specification twHRH2 defines :he block erase suspend latency. 4t this point, a Read Array command can be written ;o read data from blocks other than that which is suspended. A (Multi) Word/Byte Write command sequence can also be issued during erase suspend IO program data in other blocks. Using the (Multi) word/Byte Write Suspend command (see Section 4.1 l), a (multi) word/byte write operation can also be suspended. During a (multi) word/byte write operation with block erase suspended, status register bit 33.7 will return to "0" and the STS (if set to RY/BY#) output will transition to VOL. However, SR.6 will remain "1" to indicate block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register oits SR.6 and SR.7 will automatically clear and STS will return to VIOL. After the Erase Resume command IS written, the device automatically outputs status register data when read (see Figure 10). V,, must remain at VPPHi12,s (the same Vpp level used for block erase) while block erase is suspended. RP# must also remain at VI,. Block erase cannot resume until (multi) word/byte write operations initiated during block erase suspend have completed. 4.11 (Multi) Word/Byte Command Write Suspend The (Multi) Word/Byte Write Suspend command allows (multi) word/byte write interruption to read data in other flash memory locations. Once the (multi) word/byte write process starts, writing the (Multi) Word/Byte Write Suspend command requests that the WSM suspend the (multi) word/byte. write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the (Multi) Word/Byte Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the (multi) word/byte write operation has been suspended (both will be set to "1"). STS will also transition to High Z. Specification twHRH1 defines the (multi) word/byte write suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while (multi) word/byte write is suspended are Read Status Register and (Multi) Word/Byte Write Resume. After (Multi) Word/Byte Write Resume command is written to the flash memory, the WSM will continue the (multi) word/byte write process. Status register bits SR.2 and SR.7 will automatically clear and STS will return to V,,. After the (Multi) Word/Byte Write command is written, the device automatically outputs status register data when read (see Figure 11). V,, must remain at VPPH,,2,3 (the same V,, level used for (multi) word/byte write) while in (multi) word/byte write suspend mode. WP# must also remain at VI, or VI,. Rev. 1.9 SHARP _.- - LHF16KA7 18 4.12 Set Block Lock-Bit Command A flexible block locking and unlocking scheme is enabled via block lock-bits. The block lock-bits gate program and erase operations With WP#=V,,, individual block lock-bits can be set using the Set Block Lock-Bit command. See Table 13 for a summary of hardware and software write protection options. Set block lock-bit is executed by a two-cycle command sequence. The set block lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked). The WSM then controls the set block lock-bit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Figure 12). The CPU can detect the completion of the set block lock-bit event by analyzing the STS pin output or status register bit SR.7. When the set block lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally set. An invalid Set Block Lock-Bit command will result in status register bits SR.4 and SR.5 being set -to "1". Also, reliable operations occur only when Vcc=Vcc1,2 and VPP=VPPH,,2,s. In the absence of this high voltage, block lock-bit contents are protected against alteration. 4 successful set block `lock-bit operation requires rNP#=V,,. If it is attempted with WP#=V,L, SR.l and SR.4 will be set to "1' and the operation will fail. Set Yock lock-bit operations with WP# Command 411set block lock-bits are cleared in parallel via the Zlear Block Lock-Bits command. With WP#=V,,, Rev.1.9 SHARI= _; LHFlGKA7 Command 19 I.14 STS Configuration `he Status (STS) pin can be configured to different ;tates using the STS Configuration command. Once he STS pin has been configured, it remains in that :onfiguration until another configuration command is ;sued, the device is powered down or RP# is set to /,L. Upon initial device power-up and after exit from leep power-down mode, the STS pin defaults to IY/BY# operation where STS low indicates that the YSM is busy. STS High Z indicates that the WSM is eady for a new operation. -0 reconfigure the STS pin to other modes, the STS Configuration is issued followed by the appropriate :onfiguration code. The three alternate configurations Ire all pulse mode for use as a system interrupt. The ;TS Configuration command functions independently If the Vpp voltage and RP# must be VI,. Table 12. STS Configuration Coding Description Configuration Effects Bits Set STS pin to default level mode (RY/BY#). RY/BY# in the default OOH level-mode of operation will indicate WSM status condition. Set STS pin to pulsed output signal for specific erase operation. In this mode, STS provides low pulse at OlH the completion of BLock Erase, Full Chip Erase and Clear Block Lock-bits operations. Set STS pin to pulsed output signal for a specific write operation. In this 02H mode, STS provides low pulse at the completion of (Multi) Byte Write and Set Block Lock-bit operation. Set STS pin to pulsed output signal for specific write and erase operation. STS provides low pulse 03H at the completion of Block Erase, Full Chip Erase, (Multi) Word/Byte Write and Block Lock-bit Configuration operations. Table 13. Write Protection Operation Block Erase, . (Multi) Word/Byte Write ,,, Block Lock-Bit 0 ., , WP# v,, or V,,, VI, VI, Alternatives Effect Full Chip Erase Set Block Lock-Bit Clear Block Lock-Bits 091 X X X V,, V,H V,, V,H V,, V,w Block Erase and (Multi) Word/Byte Write Enabled Block is Locked. Block Erase and (Multi) Word/Byte Write Disabled Block Lock-Bit Override. Block Erase and (Multi) Word/Byte Write Enabled All unlocked blocks are erased, locked blocks are not erased All blocks are erased Set Block Lock-Bit Disabled Set Block Lock-Bit Enabled Clear Block Lock-Bits Disabled Clear Block Lock-Bits Enabled Rev. 1.9 .- .: - LHFlGKA7 Table 14. Status Register Definition wss 1 ECBLBS 1 WSBLBS 1 VPPS 1 5 4 3 NOTES: 2 20 WSMS 7 1 BESS 6 DPS 1 R 0 1 1 SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS STATUS 1 = Error in Erase or Clear Bloc1 Lock-Bits 0 =iSuccessful Erase or Clear Block Lock-Bits SR.4 = WRITE AND SET BLOCK LOCK-BIT STATUS 1 = Error in Write or Set Block Lock-Bit 0 = Successful Write or Set Block Lock-Bit SR.3 = V,, STATUS 1 = V,, Low Detect, Operation Abort O=V,,OK SR.2 = WRITE SUSPEND STATUS 1 = Write Suspended 0 = Write in Progress/Completed SR.1 = DEVICE PROTECT STATUS 1 = Block Lock-Bit and/or WP# Lock Detected, Operation Abort 0 = Unlock SR.0 = RESERVED FOR FUTURE'ENHANCEMENTS Check STS or SR.7 to determine block erase, full chip erase, (multi) word/byte write or block lock-bit configuration completion. SR.6-0 are invalid while SR.7="0". If both SR.5 and SR.4 are "1 "s after a block erase, full chip erase, (multi) word/byte write, block lock-bit configuration or STS configuration attempt, an improper command sequence was entered. SR.3 does not provide a continuous indication of V,, level. The WSM interrogates and indicates the V,, level only after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration command sequences. SR.3 is not guaranteed to reports accurate feedback only when V,,#V,,,,,z.s. SR.l does not provide a continuous indication of block lock-bit values. The WSM interrogates block lock-bit, and WP# only after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set and/or WP# is not V,,. Reading the block lock configuration codes after writing the Read Identifier Codes command indicates block lock-bit status. SR.0 is reserved for future use and should be masked out when polling the status register. SMS 7 R 6 Table 14.1. Extended Status Register Definition R R R R 5 4 3 NOT&: 2 R 1 R 0 XSR.7 = STATE MACHINE STATUS 1 = Multi Word/Byte Write available 0 = Multi Word/Byte Write not available XSR.G-O=RESERVED FOR FUTURE ENHANCEMENTS After issue a Multi Word/Byte Write command: XSR.7 indicates that a next Multi Word/Byte Write command is available. XSR.G-0 is reserved for future use and should be masked out when polling the extended status register. Rev. 1.9 SHARI= .<~ LHFlGKA7 21 i 24 Start write 70H Block Address Read Read Stata Register Data-7ol-l Addr=X Data-DOH Adds-Within Block to be Erased I Status Register Data Repeat for subsequent block erasures. Full status check can be done after each block erase or after a sequence of block erasures. Write FFH after tie last operation to place dwico in mad array mode. FULLSTAlUSC~ECKPROCEDURE Read Status Register Data(Sae Above) Standby Check SR.3 l-Vpp Enor Detect Chedt SR.1 I-Device Protect Detect WP#-VIL,Bkxk Lock-Bit is Set Only required for systems implemenbng lock-bit con~@uration Check SR.4.5 Both l=Command Sequence Error Check SR.5 l=Block Erase Error Device Protect Ertvr Standby Block Erase Error SRs.SR.4.SR.3 and SR. 1 are only cleared by the Clear Status Register Command in cases where multiple blocks are erased before full statUs is checked. If error is detected. clear the Status Register before attempting retry or other error recovery. Block Erase Successful Figure 5. Automated Block Erase FlOWChart Rev. 1.9 SHARI= _.- LHFlGKA7 22 .i c r start f 1 I Bus OpWlO" Command Comments wlite Read Status Register Data7OH Add-X Read Status Register Data Standby Chedt SR.7 l.WSM Ready OIWSM Busy Full Chip Erase SbJP Full Chip Ease Confin Data=3OH Addr-X Data-DOH Ad&X write write Read Status Regtster Data standby Check SR.7 l=WSM Ready OIWSM Busy Full stams check can be done after each full chip erase. Write FFH after tie last operation to place device in read army mode. Full Status Check if Desired FIJU STATUS CHECK PROCEDURE Bus OpedfO" Command Commenb Standby Check SR.3 l=Vpp Enor Detect Check SR.4,5 Both l=Ccmmand Standby Sequence Error Command Sequence Error Standby- Check SR.5 l=Full Chip Erase Error SRS,SR.4,SR.3 and SR.l am only dewed by the Clear Status Register Command in cases whew multiple blocks are erased before full status is chedmd. If error is detected, clear the Status Register before attempting retry or other error recovery. Figure 6. Automated Full Chip Erase Flowchart LRev. 1.9 SHARI= _- LHF16KA7 23 25 Write 70H Write 40H or 10H. AddreSS Comments Data-70H AddrEX Stabs Register Data Check SR.7 1.WSM Ready O-WSM Busy DataYdOH or 10H Add-Location to Be Written c Read standby Standby Dewce Protect Etmr Standby DateData to 5a Written Addhlocatfon to Se Wtitton Status Register Data Check SR.7 1-WSM Ready O-WSM Busy Repeat for subsequent w-or&byte writes. SR full status check can be done after each wordlbyte wtite, or after a sequence of wodyte writes. White FFH after the last word/byte write operation to place device in read array mode. Complete FULL STATUS CHECK PROCEDURE Read Status R@ster Data(See Above) Check SR.1 l-Device Protect Detect WPb-V~@xk Lock-Bit is Set Only required for systems implementing lock-bit configuration Check SR.4 l-Data Write Error Word/Byte write Successful SR.4.SR.3 and SR.1 are only cleared by the Clear Status Register command in casw where multiple locations are written before full stahls is checked. If error is detected. clear the Status Register before attempbng retry or other error recovery. Figure 7. Automated Word/byte Write Flowchart Rev. 1.9 SHARI= LHF16KA7 Bus operation Read Extend status Register Command Comments write S-P ~~16 WordlByte Wlite Date=EBH Add&tart Address Read Extmded Status Register Data Standby Check XSR.7 1-Multi Word/Byte Write Ready 01Multl Word/Byte Write Busy Data-Word or Byte Count (N)-1 Add&tart Address Data-Buffer Data Addr=Start Address Data-Buffer Data AddrpDewce Address Deta=DOH Addr=X Write (Note0 Writ9 (Note2.3) Wnte (Note4.5) Start Address Write Read Status Register Data Check SR.7 1=WSM Ready o=WSM Busy Standby Device Address 1, Byte or word count values on Dt& am loaded into the count register. 2. Write Buffer contents will be programmed at the start address. 3. Align tie start address on a Write Buffer boundary for maximum programming performance. 4.The device aboris the Multi Word/Byte Write command if the current address IS outside of the original block address. 5.The Status Register indicates a" `improper command sequence if the Multi Word/Byte command is aborted. Follow this with a Clear Status Rqster command. SR full status check can be done after each multi wordlbyte write, or after a sequence of multi wordmyie writes. Write FFH alter the last multi wordmyte write operation to place device in mad army mode. Read Status Figure 8. Automated Multi Word/Byte Write Flowchart Rev. 1.9 SHARI= LHF16KA7 FULL STATUS CHECK PROCEDURE FOR MULTI WORD/BYTE WRITE OPERATION Bus OpwrIion StandbY Command Comments Check SR.3 l=Vpp Error Detect Check SRI l-Device Pmtecf Detect WPbV@bck M-Bit is Set Only required for systems implementing lock-bit configuration Check SR.4,5 Both l-Command Check SR.4 l-Data Write Error standby Device Protect Error Standby Sequence Error Standby SRS,SR.4.SR.3 and SR.l am only deamd by the Clear Status Register command in cases where multiple locations are written before full status is checked. I`f error is detected, clear the Status Register before attempting retry or other error recovery. Figure 9. Full Status Check Procedure for Automated Multi Word/Byte Write Rev. 1.9 SHARP ..- LHF16KA7 26 m Commnd I Comments . A- I Road Status Register standby SR.75 1 Wlib 0 standby :-- Er;ue suspmd Df&PSOH Add-X Status Register Data AddhX Check SR.7 I -WSM Ready OCWSM Busy Chock SR.6 l&lock Erase Suspended O-Stock Erase Completed ElBe Resume DatasDOH Addr-X + (Multi) WordByte write Loop Figure 10. Block Erase Suspend/Resume Flowchart Rev. 1.9 SHARP _- LHFlGKA7 i Ella Opf&iOfl 27 Command Comments write (Multt) Wordleyte Write Suspend D&&OH Add-X Status Register Data Addr=X Check SR.7 I-WSM Ready o-WSM Eury chack SR.2 l-(Multi) woweyte SUspMd6d O-(MUHI) wordlsyta cmplatad Read w SR.7= 1 0 Standby write write Standby write Read Array DatawFFH Addr-X Read Anay locations other than that being written. Read Wtite (MuIC) Word/Byte Write Resume Data=DOH Addr-X Done c-l NO Reading Yes Figure 11. (Multi) Word/Byte Write Suspend/Resume Flowchart Rev. 1.9 SHARP LHFlGKA7 Command Comments Set Block write Lock-Bit Confirm Data-01 H. Addr-Block Address I Read I 1 Status Register Data I Check SR.7 1-WSM Ready OaWSM Busy Standby Check if Desired Repeat for subsequent block lock-bit set operations. Full status check can be done after each Mock lock-bit set operation or after a sequence of block lock-bit set operations. Write FFH after the last block lock-bit set operation to place device in read array mode. FULL STATUS CHECK PROCEDURE Command Comments Standby Check SR.3 lnVpp Error Detect CheckSR.1 l-Device Protect Detect wP#=v,L standby Standby Standby I I Check SR.4 l-Set Block Lock-Sit Error SR.S,SR.4,SR.3 and SR.l am only deared by the Clear Status Register command in cases where multiple block lock-bits are set before full statlls Ls checked. If error is detected. clear the Status Register before attempting retry or other error recovery. Figure 12. Set Block Lock-Bit Flowchart Rev. 1.9 SHARP ..- LHF16KA7 Command Comments SR.74 u 1 0 Wit0 FFH after tie Clear Block Lock-Bits operation to hce device in mad array mode. Chedc if Desired FULL STATUS CHECK PROCEDURE Read Status Register Data(s-se Above) Standby Check SR.4.5 Both l=Command Sequence Ermr Check SR.5 l=Clear Block Lock-Bits Error Standby I SR.S.SR.4.SR.3 and SR. 1 are only deamd by the Clear Status Register command. If error is det+d. clear the Status Register before attempting retry or other wmr recovery. Figure 13. Clear Block Lock-Bits Flowchart Rev. 1.9 LHF16KA7 -- 30 5 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to xcommodate multiple memory connections. ThreeJne control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system's READ#icontrol line. This assures that only selected have active outputs while memory devices deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes juring system power transitions. POWERGOOD should also toggle during system reset. STS, in default mode, is also High Z when the device is in block erase suspend (with (multi) word/byte write inactive), (multi) word/byte write suspend or deep power-down modes. 5.3 Power Supply Decoupling Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a O.lpF ceramic capacitor connected between its Vcc and GND and between its V,, and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7l.1F electrolytic capacitor should be placed at the array's power supply connection between Vc, and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 5.2 STS and Block Erase, Full Chip Erase, (Multi) Word/Byte Write and Block Lock-Bit Confjguration Polling STS is an open drain output that should be connected to V,, by a pullup resistor to provide a hardware method of detecting block erase, full chip 3rase, (multi) -word/byte write and block lock-bit configuration completion. In default mode, it transitions low after block erase,, full chip erase, [multi) word/bfie write or block lock-bit configuration commands and returns tP V,, when the WSM has finished executing the internal algorithm. For alternate STS pin configurations, see the Configuration command. STS can be connected to an interrupt input of the system CPU or controller. It is active at all times. 5.4 Vpp Trace on Printed Circuit Boards Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the V,, Power supply trace. The V,, pin supplies the memory cell current for block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. Use similar trace widths and layout considerations given to the V,c power bus. Adequate V,, supply traces and decoupling will decrease V,, voltage spikes and overshoots. Rev. 1.9 SI-IARP _.- - LHFlGKA7 31 5.5 VCC, Vpp, RP# Transitions Block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are not guaranteed if VP, falls outside of a valid VPPH1,2/3 range, Vcc falls outside of a valid Vccl,s range, or RP#=VIL. If V,, error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to V,, during block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, STS(if set to RY/BY# mode) will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power-down. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal operation is restore& Device power-off or RP# transitions to V,, clear the statusregister. The CUI latches commands issued by system software and is not altered by Vpp or CE# transitions or WSM actions. Its state is read array mode upon power-up, after exit from deep power-down or after Vcc transitions below VLkO. After block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, even after V,, transitions down to VPPLK, the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. powers-up first. Internal circuitry resets the CUI tc read array mode at power-up. A system designer must guard against spuriou: writes for Vcc voltages above VLKO when V,, i: active. Since both WE# and CE# must be low for 2 command write, driving either to V,, will inhibit writes The CUl's two-step command sequence architecture provides added level of protection against datz alteration. In-system block lock and unlock capability prevents inadvertent data alteration. The device is disablec while RP#=V,, regardless of its control inputs state. 5.7 Power Dissipation When designing portable systems, designers musi consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory's nonvolatility increases usable battery life because data is retained when system power is removed. In addition, deep power-down mode ensures extremely low power consumption even when system power is applied. For example, portable computing products and other power sensitive applications thai use an array of devices for solid-state storage can consume negligible power by lowering RP# to V,, standby or sleep modes. If access is again needed, the devices can be read following the t,,Qv and tPHWL wake-up cycles required after RP# is first raised to V,,. See AC CharacteristicsRead Only and Write Operations and Figures 17, 18, 19, 20 for more information. 5.6 Power-Up/Down Protection The device is designed to offer protection against accidental blqck and full chip , erasure, (multi) word/byte writihg or block lock-bit configuration during power transitions. Upon. power-up, the device is indifferent as to which power supply (V,, or Vco) Rev. 1.9 SHARF= .-- - LHFlGKA7 SPECIFICATIONS Ratings* *WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanen damage. These are stress ratings only. Operatior beyond the "Operating Conditions" is nc recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTES: 1. Operating temperature is for extender temperature product defined by this specification. 2. All specified voltages are with respect to GND Minimum DC voltage is -0.5V on input/output pin: and -0.2V on Vcc and V,, pins. Durin! transitions, this level may undershoot to -2.OV fo periods <20ns. Maximum DC voltage or input/output pins and Vcc is Vc.+O5V which during transitions, may overshoot to Vcc+2.0V fo periods <20ns. 3. Output shorted for no more than one second. NC more than one output shorted at a time. 6 ELECTRICAL 6.1 Absolute Maximum Operating Temperature During Read, Erase, Write and Block Lock-Bit Configuration . .. ..-40C to +85"C(1) Temperature under Bias . .. . .. .. .. .. . .. -40C to +85"C Storage Temperature .. .. . .. .. . .. .. .. . .. .. ... -65C to +125"C Voltage On Any Pin (except Vcc, V,,) . .. . .. .. . .. .. .. -0SV to V,o+0.5V(2) Vcc Suply Voltage . .. .. . .. .. .. . .. .. .. . .. .. .. .. -0.2v to +7.ov(2) V,, Update Voltage during Erase, Write and Block Lock-Bit Configuration .. .. ..-0.2V to +7.0Vt2) Output Short Circuit Current .. .. .. .. . .. .. .. .. .. .. .. . 100mAt3) 6.2 Operating Conditions Symbol TA Vc-., Vccy Temperature Parameter Operating Temperature Vcc Supply Voltage (2.7V-3.6V) Vcr. Supply Voltage (3.3ViO.3V) and Vcc ODerating Conditions Min. Max. Unit -40 +85 "C 2.7 V 3.6 V 3.0 3.6 Test Condition Ambient Temperature 6.2.1 CAPACITANCE(`) .I' Symbol Parameter C,N Input Capacitance c(y I-J- Output Capacitance NOTE: 1. Sampled, not 100% tested. T,=+25"C, Typ. 7 9 f=l MHz Max. 10 12 Unit pF pF Condition v,,=o.ov Vnr ,T=O.OV Rev. 1.9 SHARP ..- LHFlGKA7 TEST CONDITIONS 33 2.2 AC INPUT/OUTPUT yG-j(iqzzq~Z AC test inputs are driven at 2.7V for a Logic "1" and O.OV for a Logic Input rise and fall times (10% to 90%) ~10 ns. "0." Input timing begins, and output timing ends, at 1.35V. Figure 14. Transient Input/Output Reference Waveform for Vc,=2.7V-3.6V 4 ~~~~z2~~pGAC test inputs are driven at 3.OV for a Logic "1" and O.OV for a Logic Input rise and fail times (10% to 90%) cl 0 ns. "0." Input timing begins, and output timing ends, at 1 SV. Figure 15. Transient Input/Output Reference Waveform for Vcc=3.3V*O.3V 1.3v lN914 Test Configuration Capacitance Test Configuration =3.3V~0.3V, 2.7V-3.6V 1 Loading Value CJpF) 50 f CL Includes Jig Capacitance A T CL Figure 16. Transient Equivalent Load Circuit Testing Rev. 1.9 SHARP .. A LHF16KA7 34 6.2.3 DC CHARACTERISTICS DC Characteristics V,c=2.N vcc=3.3v Max. Typ. Max. Notes Typ. 1 *0.5 iO.5 1 1,396 20 100 20 100 PA 5ZO.5 rtO.5 Test Conditions Vcc=V,,Max. VIN=VCC or GND ;~"3"""""' =VcT: or GND CMOS Inputs V,,=V,,Max. CE#=RP#=Vccf0.2V TTL Inputs Vcc=VccMax. CE#=RP#=V,, RP#=GNDi0.2V &-,,,(STS)=OmA CMOS Inputs Sym. `Ll `LO Parameter Input Load Current Output Leakage Current Vcc Standby Current Unit PA PA `cc, 1 lccD `cm I, V,, Deep Power-Down Current V,, Read Current 1 1,5,6 4 20 1 4 20 mA HA Block Erase Full Chi Block Erase Full Chi Rev. 1.9 LHFlGKA7 -- DC Characteristics (Continued) V,,=2.N` V&.3V Notes Min. Max. Min. 7 -0.5 0.8 -0.5 7 2.0 kc 2.0 +0.5 Test Conditions Sym. V,, hi Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VW Output High Voltage (CMOS) Max. 0.8 Vcc +0.5 Unit V v bL VoH, VOH2 V,, Lockout Voltage during 4,7 1.5 1.5 v Normal Operations V,,,, `V,, Voltage during Write or 2.7 3.6 V Erase Operations V,,,, V,, Voltage during Write or 3.6 3.0 3.6 V 3.0 Erase Operations VppHs V,, Voltage during Write or 4.5 5.5 4.5 5.5 v Erase Operations V, kn Vcc Lockout Voltage 2.0 2.0 V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at nominal Vcc voltage and TA=+25"C. are specified with the device de-selected. If read or byte written while in erase suspend mode, 2* ICC,, and bCES the device's current draw is the sum of I,,,, or IccEs and lCCR or Iccw, respectively. 3. Includes STS. 4. Block erases, full chip erases, (multi) word/byte writes and block lock-bit configurations are inhibited when V,+V,,,k, and not guaranteed in the range between V,,Lk(max.) and V,,,, (min.), between V,,,, (max.) and VppHp(min.), between Vpp,+(max.) and VppHs(min.) and above VppHs(max.). 5. Automatic Power Savings (APS) reduces typical Iccn to 3mA at 2.7V and 3.3V Vcc in static operation. 6. CMOS inputs are either Vcc*O.2V or GNDkO.2V. TTL inputs are either V,, or V,,. 7. Sampled, net 100% tested. ' V,,,, i Rev. 1.9 SHARP _--6.2.4 AC CHARACTERISTICS LHF16KA7 - READ-ONLY OPERATIONS(`) T,=40"C to +85X 1 Notes 1 LH28F160S3H-L120 1 Min. 1 Max. Unit 36 Sym. t . .._.. I Vcc=2.7V-3.6V, Versiond4) Parameter BYTE# to Output Delay ~~~~~ BYTE# to Output in High 2 tELFL fF, FH 3 3 3 120 30 5 ns ns ns CE# Low to BYTE# High or Low NOTE: See 3.3V Vcc Read-Only Operations for notes 1 through 4. I II Sym. I I tAvnv tAvnv fF, 0" h nv fF, (Jy V ,&3.3kO.3\ Versians(4) _-_-_-.-- I, Tp40"C to +85X ( Notes 1 LH28F160S3H-Ll OO I Min. I Max. 100 100 100 AA_ tluu I I AC -vi) 0 50 0 20 0 100 30 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns _fEtic;v l?Y bH fLQV FHnV tJ, n, I Parameter 1Read Cycle Time Address to Output Delay CE# to Output Delay RP# High to uutput . - ' -. ueray ,. welay OE# to Output.&n-l... , CE# to Output in Low 2 CE# High to Output in High Z OE# to Output in Low Z ' Output Hold from Address, CE# or OE# Change, Whichever Occurs First BYTE# to Output Delay BYTE# to Output in High Z CE# Low to BYTE/# High or Low II 2 I -; 3 3 3 3 3 3 r) I FLFL FI FH NOTES: 1. See AC Input/Output Reference Waveform for maximum allowable input slew rate. 2. OE# may be delayed up to tELQv-&AI, after the falling edge of CE# without impact on 3. Sampled, not 100% tested. 4. See Ordering Information for device speeds (valid operational combinations). Rev. 1.9 SHARP _- LHF16KA7 37 - r .i Device Address Selection Address Stable tAVAV VIH Data Valid 1.11.11111 CE#(E) VIL VIH OE#(G) VIL ,.,o....mn VOH VOL 4 tAVQV b kc """""- NOTE: CE# i&defined as the latter of Cl&# and CE# going Low or the first of CEo# or CE$ going High. Figure 17. AC Waveform for Read Operations Rev. 1.9 SHARP LHFlGKA7 Device Address Selection Address Stable Data Valid 1..1.11..1 VIH CWE) VIL tAVFL=tELFL VIH OE#(G) VIL k QJIH BYTE#(F) VIL VOH VOH NOTE: CE# is defined as the latter of CEo# and CEI# going Low or the first of CEo# or CE+# going High. Figure 18. BYTE# Timing Waveforms Rev. 1.9 SHARP LHFlGKA7 6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS(`) 39 NOTE: See 3.3V Vcc WE#-Controlled Writes for notes 1 through 5. Vcc:=3.3V+0.3V, T,=40"C Versions@) Parameter to +85"C 1 Notes 1 LH28F160S3H-Ll OO ) Min. ) Max. Unit Sym. I twclr,, Write Recovery before Read Vpp Hold from Valid SRD, STS High Z WP# VI,, Hold from Valid SRD, STS High Z 2,4 z4 0 0 0 ns ns ns NOTES: 1. Read timing characteristics during block erase, full chip erase, (multi) wrod/byte write and block lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations. 2. Sampled, not 100% tested. 3. Refer to Table 4 for valid A,,,, and D,, for block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. 4. Vpp should be held at V,PH1,2j3 until determination of block erase, full chip erase, (multi) word/byte write or block lock-bit configuration success (SR.1/3/4/5=0). 5. See Ordering Information for device speeds (valid operational combinations). Rev. 1.9 SHARI= LHFlGKA7 ADDRESSES(A) NOTES: 1. Vcc power-up and standby. 2. Write erase or write setup. 3. Write erase confirm orvalid address 4. Automated erase or program delay. 5. Read stat®ister data. 6. Write Read Array command. 7. CE# is defined as the latter of CEo# and data. 1 and CE,# going Low or the first of CEo# or CE,# going High. Figure 19. AC Waveform for WE#-Controlled Write Operations Rev. 1.9 SHARP LHF16KA7 -- - 6.2.6 ALTERNATIVE I Sym. 1 CE#-CONTROLLED v ,,=2.7\1-3.6\ Versions@) Parameter WRITES(`) ~-40C to +85"C ( Notes 1 LH28F160S3H-L120 1 Min. ( Max. 1 Unit I ! h WE# Hold fr om CE# Hiah tFWF, 8 CE# Pulse Widt :h High CE# High to STS Going Low tfq+n, Write Recovery before Read fFHG, Vpp Hold from Valid SRD, STS High Z 24 WP# VIH Hold from Valid SRD, STS High Z 2,4 NOTE: See 3.3V Vco Alternative CE#-Controlled Writes for nc)tes 1 through 5. 25 100 0 0 0 ..ns ns ns ns ns clFl ( Write Cycle Time 1RP# High Recovery to CE# Going Low 2 I 100 1 I t"pFw tJJFH $-)"FH 11tFwax Vpp Setup to CE# Goi Address Setup to CE# Going High Datd Setup to CE# Going High I Address Hold from CE# High 3 50 tFClr,, hWl tnVSl Write Recovery before Read Vpp Hold from Valid SRD, STS High Z WP# V,, , Hold from Valid SRD, STS High Z 24 2,4 0 0 0 ns ns ns NOTES: 1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold and inactive WE# times should be measured relative to the CE# waveform. 2. Sampled, not 100% tested. 3. Refer to Table 4 for valid A,, and D,, for block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. 4. V,, should be held at V,,,,,z,, until determination of block erase, full chip erase, (multi) word/byte write or block lock-bit configuration success (SR.1/3/4/5=0). 5. See Ordering Information for device speeds (valid operational combinations). Rev. 1.9 SHARI= LHFlGKA7 A--ADDRESSES(A) 1 2 3 4 A- 6 VIH WE#(W) OE#(G) CE#(E) DATA(D/Q) STS(R) NOTES: 1. Vcc power-up and standby. 2. Write erase or write setup. 3. Write erase confirm orvalid address and data. 4. Automated erase or program delay. 5. Read status'register data. 6. Write Read Array command. 7. CE# is defined as the latter of CEo# and CE,# going Low or the first of CE& or CE+ going High. Figure 20. AC Waveform for CE#-Controlled Write Operations Rev. 1.9 SHARI= LHFlGKA7 .. ; RESET OPERATIONS High Z STS(R) VOL VIH RP#(P) VIL tpLPH (A)Reset High Z STS( R) VOL VIH During Read Array Mode RP#(P) 4 ML (B)Reset During Block Erase, Full Chip or Block Lock-Bit Configuretion 2.7f3.3V vcc WL VIH Erase, (Multi) Word/Byte Write RP#( P) VIL I I- (C)Vcc Power Up Timing Figure 21. AC Waveform for Reset Operation Reset AC Specifications Symbol tPLPH tPLRH t23VPH Parameter RP#/ Pulse Low Time (If RP# is tied to Vcc, this specification is not applicable) RP# Low to Reset during Block Erase, Full Chip Erase, (Multi) Word/Byte Write or Block Lock-Bit Configuration Vcc at 2.7V to RP# High Vcn at 3.OV to RP# High Notes V,.,=2.7V Max. Min. 100 vr.c=3.3v Min. Max. 100 Unit ns 1,2 3 - 100 21.5 100 21.1 IJS ns MOTES: 1. If RP# is asserted while a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration operation is not executing, the reset will complete within 1 OOns. 3. A reset time, tpHov, is required from the latter of STS going High Z or RP# going high until outputs are valid. 3. When the device power-up, holding RP# low minimum 1OOns is required after Vcc has been in predefined range and also has been in stable there. L Rev. 1.9 SHARP LHFlGKA7 -- - 44 6.2.8 BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE AND BLOCK LOCK-BIT CONFIGURATION PERFORMANCE@) Vnn=2.7V-3.6V, TA=-40"C to +85"C Vp,=3.0V-3.6V Vp,=2.7V-3.6V Notes ' Typ.(l) Max. Typ.(`) Max. 2 2 2 2 22.19 19.9 5.76 0.73 250 250 250 8.2 22.19 19.9 5.76 0.73 250 250 250 8.2 Vp,=4.5V-SSV Typ.(`) Max. 13.2 13.2 2.76 0.44 180 180 180 4.8 , Sym. tWHQVl tEHQV1 tEHQVl twHQyl Parameter Word/Byte Write Time (using W/B write, in word mode) Word/Byte Write Time (using W/B write, in byte mode) Word/Byte Write Time write) (using multi word/byte Block Write Time (using W/B write, in word 4 mode) Block Write Time Unit ps us vs s NOTE: See 3.3V V&Block Erase, Full Chirj Erase, (Multi) Word/Byte Write and Block Lock-Bit Configuration for notes 1 through 3. Performance Rev. 1.9 SHAl?I= _-Voc=3.3V+0.3V, Sym. tw,,ov, tF,,,,,,, PHQVl LHFlGKA7 T,,=-40C to +85"C Vp,=3.0V-3.6V Notes Typ.(`) 1 Max. I 2 21.75 250 2 2 I r) I 19.51 5.66 nvr, I .L" Parameter Word/Byte Write Time (using W/B write, in word mode) Word/Byte Write Time (using W/B write, in byte mode) Word/Byte Write Time (using multi word/byte write) , Block Write Time (using W/B write, in word mode) I Block Write Time (using W/B write, in byte mode) I Block Write Time (using multi word/byte write) Block Erase Time \ vpp=4.5v-5.5v Typ.(`) 1 Max. I 12.95 180 12.95 2.7 1 1 0.43 0.85 1 1 180 180 4.8 10.9 1 1 Unit IJS IJS P s s 1 /I Fwr,v, 250 250 I a.2 i5.5 -r 10 320 250 10 10 21 .l II II II II F FHnV7 I Q L I , 4 r)n I ".J" 0.55 17.6 I 2 0.41 13.1 12.95 0.41 6.6 12.3 10 320 180 10 9.3 17.2 S S Full Chip Erase Time Set Block Lock-Bit Time Clear Block Lock-Bits Time Write Suspend Latency Time to Read Erase Suspend Latency Time to Read 2 2 `wHQvs bg iwHQV4 FHOVA 21.75 0.55 7.1 15.2 IJS S :wHnHt FHRHI LJS IJS pHnH2 FHRH7 NOTES: 1. Typical values measured at TA=+25"C and nominal voltages. Assumes corresponding block lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. Sampled but not 100% tested. Rev. 1.9 SHARP _7 ADDITIONAL .. L INFORMATION LHFlGKA7 46 7.1 Ordering Information Product line designator for all SHARP Flash products I I I [L/H12/8)FIl~6~01S13~H~T~-1L~l~O~Al I IJ Device Density 160 = 16-Mbit Architecture S = Regular Block 4 Power Supply Type 3 = Smart 3 Technology Operating Temperature] Blank = 0C - +7O"C H = -40C - +85"C ACTS Speed (ns) 1O:l OOns (3.3V), 120ns (2.7V) 13:130ns (3.3V), 150ns (2.7V) Package T = 56-Lead TSOP R = 56-Lead TSOP(Reverse Bend) NS = 56-Lead SSOP B = 64-Ball CSP D = 64-Lead SDIP Option 1 Order Code LH28F160S3HT-Ll OA Valid Operational Combinations V,,=2.7V-3.6V v(--=3.3v+o.3v 5OpF load, 5OpF load, 1.35V I/O Levels 1 SV l/O Levels LH28F160S3H-L120 LH28F160S3H-Ll OO .I' Rev. 1.9 SHARP LHF16KA7 Flash memory LHFXKXX family Noises having generated Such noises, To protect operating appropriate: 1) Protecting Setting operation into, data in specific block block and pulling feature, the flash section) WP# low disables the writing memory space can be divided and data section(unlocked through refer the software. a level Data Protection the limit conditions specified in the specification may be interpreted may be as false systems designs, as 47 exceeding operating under specific on some systems. when induced onto WE# signal undesired the data stored in the flash or power supply, memory against commands, causing memory updating. unwanted overwriting, write protect with the flash memory should have the following the lock bit for example, of the desired By using this the program on that block. section(locked set t ion). By controlling For further (See chapter WP#, desired information 4.12 and 4.13.) through Vpp voltage), write operation on the intheblocksarecompletely (See chapter 6.2.3. > blocks can be locked/unlocked block bit, on setting/resetting to the specification. 2) Data protection When the level flashmemory write protected. of Vpp is lower than VPPLK (lockout ..' voltage, through operation refer RP# to the specification. is disabled. All blocks are lockedandthedata For the l&kout 3) Data protection transition, blocks. write When the RP# is kept low during power up and power down sequence such as voltage memory is disabled, write protecting 5.6 and 6.27. all ) on the flash refer For the detai 1s of RP# control, to the specification. (See chapter Rev 1.9 SHARP _~. -- - LHF16KA7 48 LH28F16OSXX-LXX Flash MEMORY ERRATA 1. Multi Word/Byte Write Operations . PROBJ,EMt When two planes of 32-byte page buffer areboth in full and first buffer data are being written to the flash array, the extended statusregister bit XSR.7 may be erroneously set to "l", which indicates the Multi Word/Byte Write command is available. woRKARouND (1) Usk One Page Buffer After writing the data by the Multi Word/Byte Write command, the status register must be read to check the bit SR.7. At this point, the device is in read status register mode whether the Read Status Register command is written or not. After the status register bit SR.7 is set to "l", the next Multi Word/Byte Write command will be available. (2) Use Two Page Buffers After writing the data in two planes by the Multi Word/Byte Write command, the statusregister must be readto check the bit SR.7. At this point, the device is in readstatusregister mode whether the Read StatusRegistercommand is written or not. After the statusregister bit SR.7 is setto "1") the next Multi Word/Byte Write command will be available. .,l' SHARP _-- - LHF16KA7 49 LH28F160SXX-LXX Flash MEMORY ERRATA Use One Page Buffer Start r.. ____ __ _ _ __ ___ _ ___ __ _ ____ . .. ._ __ ___ ___ . __ _ ___ __. .. . .. .. - ~~-~~--~~~: Command 1 Write 1 Read Sequence E8H XSR Start Address SHARP RELATED DOCUMENT Document No. AP-OOI-SD-E AP-oodFT-E AP-O07-SW-E NOTE : I. Inmational INFORMATION(`) Document Name Flash Memory Family So&are Drivers Data Protection Method of SHARP Flash Memory R.P#, vpp Ekctfic PotentiaI switching circuit customers should contact their local SHARP or distribution sales office. SHARP PRELIMINARY 3l is JI ASE PLANE g DETAIL A $6 i J(E i TSOP56-P-1420 !I - Ftt-AZ LEAD FINISH 4a RA'iiINGNO. ! AA1115 UNIT ; TIN-U I* 1%flShlr"f%t& d95SttrrWf3. ! PLATING NOTE Plastic body dimensions do not include of resin. i i mm burr |
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